This invention relates to active clamp circuits for providing electrical overshoot and undershoot protection, particularly in double gate silicon on insulator (SOI) integrated circuit applications.
Over the years, digital circuits, and the voltage levels associated therewith, have decreased in size in order to keep up with modern technology. In so doing, modern digital circuits which operate at one voltage level may need to transfer signals to and/or receive signals from circuits operating at other voltage levels. Clamping circuits have been introduced in the art to allow circuits to transfer signals to and/or receive signals from circuits operating at differing voltages by partially terminating and protecting each circuit from voltages that are outside its operating range.
Clamping circuits maintain voltages within an acceptable range by controlling electrical overshoot (positive) and undershoot (negative) at the signal input of a digital circuit to provide a reliable logic signal under adverse and noisy conditions. In an ideal system, the input voltage to each element in a digital circuit will be in only one of two distinct logic states, either an upper digital voltage or a lower digital voltage. The upper digital voltage (or positive terminal) of the power supply (referred to herein as Vdd) corresponds to the digital ones of the circuit and is typically +5 volts and may be 3.3, 2.5, 1.8, 1.2 volts or even lower in newer designs. The lower digital voltage of the power supply (referred to herein as Vss) corresponds to the digital zeros of the circuit and is typically at ground potential which may be zero volts.
Ideally, the input voltage switches instantly between the up state and the down state, never going above the upper voltage nor below the lower voltage, and spending substantially no time at any intervening voltage between the two states. However, in real circuits the input voltage generally takes a finite amount of time to switch between the two logic states wherein the input voltage often exceeds the upper limit, i.e., overshoots the voltage, and oscillates (or rings) around this new voltage before settling down. Clamping circuits have been designed to minimize such ringing as it can seriously degrade the circuit""s performance. Typically, a good clamping circuit dampens ringing and reduces noise so that the signal at the input remains at or near one of the two desired voltage states (Vdd or Vss) and switches between these two states quickly and cleanly.
Improved clamping performance comes about by supplying or draining current as quickly as possible to/from the network at the input to the circuit being clamped whenever the voltage at the input exceeds or falls below the two desired voltage states. In order to supply sufficient current, the clamping circuit should have low impedance and a low reflection coefficient in the vicinity of the upper and lower voltages corresponding to the two digital logic states. However, in order to maximize switching speed between the two logic states, the impedance of the clamping circuit and the reflection coefficient should be very high during switching for the brief time when the input voltage is between the upper and lower digital voltages. Currently used passive clamping circuits are unable to effectively meet these opposing requirements for the highest performance applications.
Typically, in a passive clamping circuit, any excess signal voltage on the input is pulled towards or clamped to the positive Vdd supply voltage while any lower signal voltage state is pulled towards or clamped to the lower voltage supply Vss or ground. As transistors continually decrease in size and the upper digital voltage of the power supply (Vdd) associated therewith decreases, i.e., 1.2 volts or even lower in newer designs, passive clamping circuits are unable to effectively supply or drain current whenever the voltage at the input exceeds or falls below the two desired voltage states.
For example, a typical prior art 5.0 volt system has used a passive clamping circuit in which one diode, having a 0.7 turnout voltage, is placed between the input terminal and Vss (zero volts) and another is placed between the input and Vdd (5.0 volts). The diode between the input terminal and Vdd will conduct when the voltage at the input terminal rises sufficiently above the upper digital voltage to turn on the diode. Thus, this diode limits the input voltage to about 0.7 volts above the desired maximum input voltage, or to about 5.7 volts, but permits 0.7 volt ringing around the upper digital voltage. The second diode is positioned between the input terminal and Vss and conducts when the voltage at the input terminal falls one diode drop below the lower digital voltage (usually zero volts). This prevents ringing in excess of about 0.7 volts, but still permits ringing having a magnitude less than the value needed to turn on the passive diode clamp.
Passive clamp circuits of this type work in 5.0 volt systems because the amplitude of the ringing is relatively small compared to the difference between the upper and lower digital voltages. However, in modern systems having lower maximum input voltages and thus smaller differences between the upper and lower digital voltages, passive clamp circuits of this type are not effective. The 0.7 volt degrades into the noise tolerance of the lower voltage system, such as a 3.3 volt system. Moreover, in 2.5, 1.8, 1.2 and even lower volt systems, such ringing is unacceptable as it produces erratic operation in noisy environments. For example in a 1.0 maximum input volt system, the amplitude of the ringing is large compared to the difference between the upper and lower digital voltages as the diode providing 0.7 volts above the maximum input voltage of 1.0 volt would almost double such voltage, i.e., to about 1.7 volts, causing erratic operation. Accordingly, lower voltage designs need even more careful control over the input signal to prevent erratic operation due to ringing or other noise at the input.
Performance is also improved by driving the input terminal voltage to the upper digital voltage via a connection to Vss when the input voltage is too high (above the upper voltage which is usually Vdd) and by driving the input terminal voltage to the lower digital voltage via a connection to Vdd when the input terminal voltage is too low (below the lower digital voltage which is usually Vss). This increases the speed at which the clamping circuit operates as compared to prior art designs which drive excessively low voltages through a connection to the low voltage supply (Vss) and excessively high voltages through a connection to the high voltage supply (Vdd).
Another requirement for digital circuits is some form of electrostatic discharge (ESD) protection. Generally, separate ESD protection circuits are provided at the input of the circuit to limit the voltage that can be imposed on the circuit at the input terminal even when the circuit is unpowered. It would be desirable if the ESD protection could be incorporated into the clamping circuit. The ability to rapidly supply or drain current is important for both clamping and ESD protection. Older designs for clamping circuits that use current limiting resistors do not provide good ESD protection.
As metal oxide semiconductor technology has improved, MOS devices have been constructed with shorter gate lengths, thinner gate oxides and faster response times. As the gate oxide becomes thinner, the device must be powered with a lower voltage power supply to avoid breakdowns and leakage. Lower power supply voltages are also advantageous in reducing power consumption, decreasing heating, and increasing speed through smaller voltage swings. Good ESD protection for lower voltage designs is critical.
To avoid some of the problems with older MOS devices, source terminated drivers have been used in MOS circuits to lower the drive current of the driver into the net. Unfortunately, this increases delay and slows circuit response. Another problem with this solution is due to complex process tolerance requirements during construction of MOS devices. This results in poor control of the driver output impedance which also causes ringing.
Silicon-on-insulator (SOI) technology further improves the speed at which transistors perform and reduces the voltages required. The SOI layer not only reduces the capacitance of the semiconductor switch so it operates faster, but also eliminates the xe2x80x9cbody effectxe2x80x9d which causes lower current and lower performance in bulk CMOS technology. Due to the SOI characteristics, it can operate at lower power than MOS technology.
For SOI designs and low voltage MOS designs, an active clamping circuit is needed, particularly in high performance low voltage designs where the clamp must hold the ringing to much less than the 0.7 volt limit of a passive diode clamp. Active clamp circuits employing transistors instead of diodes are known, but heretofore they have been bipolar in design, and thus are not suited for construction with the remainder of the MOS circuitry.
Another difficulty with prior art designs is that they have been similar to the passive diode clamp circuit described above. They have clamped the high logic signal to the higher Vdd power supply and the lower voltage logic signal to the lower voltage supply Vss. While this is functional, it cannot supply current as quickly to damp out ringing and noise as can a circuit designed according to the present invention. A further problem with prior art clamping circuit designs is the use of current limiting resistors which slow the clamping circuit response time and make them unsuitable for modern high speed MOS field effect transistor (MOSFET) circuits and SOI circuits.
As transistors continue to decrease in size, both power supply voltages and signal voltages associated therewith also continue to decrease. However, as such signal voltages decrease the detectable range of signals also decrease therewith, making it more and more difficult to maintain voltages within an acceptable range by controlling electrical overshoot and undershoot.
Accordingly, as devices become smaller and more sensitive, there continues to be a need for providing reliable logic signals of digital circuits under adverse and noisy conditions. There also continues to be a need for low power consumption designs for active clamping circuits and for circuits that may be turned off remotely, particularly during testing operations.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a clamping circuit specifically adapted for MOS, SOI circuits and triple well technologies that turns on immediately at the desired clamping voltage, instead of at a diode voltage drop away from the desired voltage.
It is another object of the present invention to provide a clamping circuit that has high impedance during switching, for high switching speed, but low impedance when clamping (for rapid reduction of any ringing).
A further object of the invention is to provide a clamping circuit that may be switched on and off.
Still another object of the present invention is to provide a clamping circuit which has low power consumption.
It is yet another object of the present invention to provide a clamping circuit that provides ESD protection at the input of an attached circuit.
Another object of the present invention is to provide an active clamping circuit which also operates when unpowered to provide ESD protection.
Still another object of the present invention is to provide a clamping circuit suitable for use with low voltage power supply systems, including 2.5 volt, 1.8 volt and lower voltage power supply systems.
Another object of the invention is to provide a clamping circuit which provides compatibility between two systems of different voltage levels.
Still another object of the invention is to provide a clamping system which has the capability of selecting more than one voltage level to clamp.
Yet another object of the invention is to synthesize the ESD function and active clamping function into a common circuit to provide area reduction.
Another object of the present invention is to provide lower capacitance.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.
The above and other objects and advantages, which will be apparent to one of skill in the art, are achieved in the present invention which is directed to, in a first aspect, a double-gated clamping circuit having an input terminal for receiving an input voltage, a first power supply terminal for connection to a first supply voltage, and a second power supply terminal for connection to a second supply voltage, the second supply voltage being less than the first supply voltage.
A first transistor having a first and a second control lead is serially connected between the first power supply terminal and the input terminal and a second transistor also having a first and a second control lead is serially connected between the second power supply terminal and the input terminal. A reference circuit is coupled to the first and second control leads of the first and second transistors for maintaining at least first and second preselected reference voltages at the first and second control leads of the first and second transistors, respectively. The first reference voltage from the reference circuit is less than the second reference voltage. Preferably, at least one of the first and second transistors is a dynamic threshold voltage MOS field effect transistor.
Additionally, at least one staging circuit may be coupled to the first and second control leads of at least one of the first and second transistors to determine a selected reference voltage at the control lead to which the at least one staging circuit is coupled.
The first control leads of both the first and second transistors are coupled to a first reference circuit while the second control leads of both the first and second transistors are coupled to a second reference circuit. In so doing, the first and second reference circuits maintain the preselected reference voltages at the first and second control leads.
In an embodiment of the invention, the first and second reference circuits maintain first, second, third, and fourth preselected reference voltages at the first and second control leads of each the first and second transistors. In such embodiment, the first and third preselected reference voltages are at the first and second control leads of the first transistors, respectively, and the second and fourth preselected reference voltages are at the first and second control leads of the second transistors, respectively. The first reference voltage being less than the second reference voltage and the third reference voltage being less than the fourth reference voltage.
Preferably, the first and second transistors each having the first and second control leads are a first double-gated transistor having a front gate and a back gate and a second double-gated transistor having a front gate and a back gate.
In accordance with an embodiment of the invention, the first and second control leads of the first transistor may be electrically coupled to each other while the first and second control leads of the second transistor are also electrically coupled to each other. Still further, the first and second control leads of the first and second transistors may be symmetrical, or alternatively, asymmetrical.
The first reference voltage is adjusted to switch on the first transistor and connect the input terminal to the first power supply terminal when the input voltage passes a first limit voltage. The second reference voltage is adjusted to switch on the second MOS field effect transistor and connect the input terminal to the second power supply terminal when the input voltage passes a second limit voltage.
The first reference voltage is preferably adjusted to the second supply voltage plus the threshold voltage of the first MOSFET and the second reference voltage is preferably adjusted to the first supply voltage minus the threshold voltage of the second MOSFET.
In the preferred embodiment of the invention, the first and second transistors are constructed as dynamic threshold voltage MOS field effect transistors (DTMOS). The use of DTMOS devices, with appropriate connection of the body of the DTMOS provides a circuit with significantly improved performance.
In the DTMOS design the DTMOS field effect transistors have bodies constructed on the substrate which can be electrically isolated from other devices on the substrate. This may be accomplished through the use of silicon-on-insulator (SOI) substrates, FINFET designs or through triple well implementations in which the transistor is electrically isolated via the diode junctions formed by the multiple wells.
The instant double-gated clamping circuit may be in combination with a circuit having a circuit input whereby the input terminal of the double-gated clamping circuit is directly connected to the circuit input. In so doing, the double-gated clamping circuit prevents overshoot and undershoot of the input voltage relative to desired input voltages at the circuit input. Alternatively, the double-gated clamping circuit is directly connected to the circuit input whereby the double-gated clamping circuit provides electrostatic discharge protection to the input terminal of the circuit.
In accordance with the invention, the reference circuit comprises at least one reference circuit having a third transistor coupled to the second power supply terminal and a fourth transistor coupled to the first power supply terminal. The third and fourth transistors are serially connected between the first and second power supply terminals.
In another aspect, the instant invention provides a double-gated clamping circuit having an input for receiving an input voltage and a double-gated transistor circuit for clamping the input at both a first voltage and at a second voltage.
The double-gated transistor circuit includes a first double-gated transistor coupled to a first power supply terminal at the first voltage and to the input. The first double-gated transistor has a first and a second gate directly coupled to each other to connect the input to the first power supply terminal through the first transistor when the first transistor is turned on.
The double-gated transistor circuit also includes a second double-gated transistor coupled to a second power supply terminal at the second voltage and to the input. The second double-gated transistor has a first and a second gate directly coupled to each other to connect the input to the second power supply terminal through the second transistor when the second double-gated transistor is turned on.
A reference circuit is coupled to the first and second coupled gates of the first double-gated transistor and to the first and second coupled gates of the second double-gated transistor for maintaining preselected constant gate voltages at the first and second gates of each of the first and second double-gated transistors. The gate voltages are independent of the input voltage.
Alternatively, the first and second gates of each of the first double-gated transistors may not be coupled to each other whereby a first reference circuit is coupled to the first gates of each of the first and second double-gated transistors for maintaining preselected constant gate voltages at the first and second gates of each of the first and second double-gated transistors. A second reference circuit is coupled to the second gates of each of the first and second double-gated transistors for further maintaining the preselected constant gate voltages at the first and second gates of each of the first and second double-gated transistors.